Architectures

See how Altifigence workflows fit into FPGA deployment and ASIC implementation.

Overview

These pages show where Altifigence tools fit into common FPGA and ASIC flows. Use them as workflow maps, then open the product or CLI guide for exact commands.

Available Workflows

Workflow	Covers
Edge FPGA deployment	RTL preparation, verification, implementation, deployment, and runtime checks
ASIC process	RTL readiness, synthesis, physical implementation, analysis, and signoff

How to read these notes

Use the FPGA and ASIC pages to identify the input, output, and review point at each stage. Product setup lives under Products, and command syntax lives under Developers.