Edge FPGA deployment

Follow the stages from an RTL project to a programmed edge FPGA.

Overview

An edge FPGA workflow turns reviewed RTL into a target-specific build, programs the board, and checks the running design.

Workflow

Stage	Input	Output to review
Prepare	RTL, constraints, target profile, and project configuration	Validated project boundary and diagnostics
Verify	Tests, assertions, expected behavior, and selected runner	Logs, failures, coverage, and evidence
Implement	Target device, constraints, and supported vendor toolchain	Reports and a target-specific artifact when successful
Deploy	Built artifact, board connection, and runtime configuration	Device programming state and runtime readiness
Observe	Workload and measurement method	Logs, traces, results, and provenance

Where Implementation Runs

Implementation can run locally, on customer-managed infrastructure, or on an enabled Altifigence-managed runner. Before starting, check the selected runner, region, installed toolchain, account permission, and files that will be sent.

What to Keep

Keep the source revision or digest, target, constraints, tool versions, runner, timestamps, build report, artifact identity, and observed runtime result. A generated project skeleton is only a starting point, not a programmed device.