Edge FPGA deployment
Follow the stages from an RTL project to a programmed edge FPGA.
Overview
An edge FPGA workflow turns reviewed RTL into a target-specific build, programs the board, and checks the running design.
Workflow
Stage | Input | Output to review |
|---|---|---|
Prepare | RTL, constraints, target profile, and project configuration | Validated project boundary and diagnostics |
Verify | Tests, assertions, expected behavior, and selected runner | Logs, failures, coverage, and evidence |
Implement | Target device, constraints, and supported vendor toolchain | Reports and a target-specific artifact when successful |
Deploy | Built artifact, board connection, and runtime configuration | Device programming state and runtime readiness |
Observe | Workload and measurement method | Logs, traces, results, and provenance |
Where Implementation Runs
Implementation can run locally, on customer-managed infrastructure, or on an enabled Altifigence-managed runner. Before starting, check the selected runner, region, installed toolchain, account permission, and files that will be sent.
What to Keep
Keep the source revision or digest, target, constraints, tool versions, runner, timestamps, build report, artifact identity, and observed runtime result. A generated project skeleton is only a starting point, not a programmed device.
Prepare a reproducible baseline
Record board revision, FPGA part/package/speed grade, voltage and clock sources.
Save RTL, constraints, testbench and expected reset/I/O behavior under one revision.
Run simulation and inspect assertions, warnings and the relevant waveform intervals.
Select a vendor implementation toolchain that supports the exact device and required IP licences.
Check clock, pin and timing constraints before implementation; unresolved clocks or pins need review.
Review implementation before programming
Read utilization, clock/timing reports, unconstrained paths, I/O assignments and severe warnings. Confirm that the produced programming artifact matches the source revision, target device and constraints. A generic cell count or DDS structural analysis is useful earlier in the flow but cannot replace these target-specific reports.
Check the running board
Follow the board vendor’s power and programming instructions. Confirm the exact connected device before loading an artifact, then test reset, clock, basic I/O and a known workload. Record the programmed artifact hash and actual output. Measure latency, throughput or power with a stated workload and method; simulation or synthesis alone does not supply those board measurements.