First RTL simulation in Digital Design Studio

First RTL simulation in Digital Design Studio for Windows. Open the counter example, run its testbench on your PC and read the waveform.

Digital Design Studio for Windows: this tutorial runs a testbench on your PC with the OSS CAD Suite simulators, which the app downloads and installs only when you ask. See Downloads for the published packages.

Overview

Digital Design Studio includes a small example project: a 4-bit counter (rtl/counter.sv) and its testbench (tb/counter_tb.sv). In this tutorial you open the example, install the simulators once, press Run and read the waveform. The simulation runs on your PC and does not start a Cloud job.

You need:

The Digital Design Studio Windows app on Windows x64.
An Altifigence account is optional: you can run the simulators without signing in, and the Windows app does not need a device licence.
An internet connection for a one-time download of about 574 MiB from GitHub. About 226 MiB stays on your PC after installation.

Install and sign in

Download the Windows app from Downloads and install it as described in the Windows installation guide.
Start Digital Design Studio. On Sign in to Digital Design Studio, choose Continue with Altifigence and finish signing in in your browser.
If you choose Continue without login instead, you can still open, edit and run the example; sign in later when you need account services such as Cloud or AI.

Open the counter example

When a new user starts the app on a PC for the first time, the counter example opens by itself after you sign in or continue without login. The app opens the testbench tb/counter_tb.sv and the RTL simulation tab.

The example does not open by itself if Digital Design Studio was used on this PC before (for example a saved sign-in, a recent or Academy project, or a saved window), if the app was started to open a specific project, or if the organization you signed in to already has Cloud projects. To open it yourself:

At the top of the navigation panel, open the environment menu and choose Local.
On Projects on this PC, choose Open example. If a project on this PC is already open, choose Local below the project list to return to this page.

Save your edits and let running tasks finish first: the app does not switch projects while there is unsaved work or a running task.

The example is your own copy, created once in the app's data folder. Opening it again keeps your changes.

File	Contents
`rtl/counter.sv`	A 4-bit counter with an asynchronous active-low reset (`rst_n`). It counts while `enable` is high.
`tb/counter_tb.sv`	The testbench. It resets the counter, enables it for 20 clock cycles, checks that the count wrapped to 4 and writes `counter_tb.vcd`.
`README.md`	A short description of the example.
`.gitignore`	Keeps the `.alti/` folder, which holds run results, out of Git.

Install the OSS simulators (once)

Digital Design Studio does not bundle the simulators. When you ask, it downloads the official YosysHQ OSS CAD Suite build 2026-10-09, checks the download against a pinned SHA-256 and installs only the files that Icarus Verilog, Verilator and GTKWave need.

In the RTL simulation tab, keep Testbench selected. Until the simulators are installed, the panel shows "The OSS CAD Suite simulator extension is not installed. Run installs it first."
Press Run. In Install the OSS CAD Suite simulators?, choose Download and install. Not now closes the dialog without installing anything.
The dialog shows the download, the SHA-256 check and the installation. Cancel stops it; the partial download is kept and resumes next time.
When the installation finishes, the run starts.

You can also install the simulators in advance: open Plugins, select OSS CAD Suite simulators and choose Install. Later runs on this PC use the same installation.

Run the testbench

Check the panel: Testbench is counter_tb · tb/counter_tb.sv, Simulator is Icarus Verilog and Waveform format is VCD. Below them, the panel shows "2 source file(s) · top counter_tb".
Press Run. Run first saves changed .v, .sv, .svh and .vh files. It then compiles every .v and .sv file in the project, except files under .alti/, .altifigence/, .git/ and node_modules/, with the selected testbench as the top module.
When the run passes, the panel shows Passed with the simulator version and the run time, and opens the waveform below it.
Expand Simulator log to see the compiler and simulator output. The testbench prints counter_tb: PASS count=4 at 260 ns.

Read the result

The clock period is 10 ns. The testbench changes its inputs on falling clock edges, and the counter counts on rising edges. The waveform shows:

Time	Signals
0–20 ns	`rst_n` is low. With Icarus Verilog, `count` is unknown (`x`) until the rising edge at 5 ns resets it to 0.
20 ns	`rst_n` goes high.
30 ns	`enable` goes high.
35–225 ns	`count` increases by 1 at each rising edge of `clk`, wraps from 15 to 0 at 185 ns and reaches 4 at 225 ns.
230 ns	`enable` goes low; `count` stays at 4.
260 ns	The testbench checks `count`, prints the PASS line and ends the simulation.

The status line shows how the run ended:

Status	Meaning
Passed · …	The simulator finished with exit code 0 and the testbench log did not report a failure.
Failed (exit code N) · …	The simulator finished with a nonzero exit code, for example after a compilation error. Read Simulator log for the compiler or testbench message. When Digital Design Studio rejects the input before simulation, the log explains the rejected path or setting; an absent simulator exit code is not a completed run.
Testbench reported a failure · …	The simulator finished with exit code 0, but the testbench log reported a failure. Read the failure message in Simulator log.
Stopped after the time limit · …	The run took longer than 2 minutes, the limit for runs from this panel.
Cancelled	You pressed Cancel during the run.

Each run is kept in its own folder under the project's .alti/sim/, with the waveform and a receipt.json. The receipt records the simulator log and version, the OSS CAD Suite release and the SHA-256 of every source and included file. Digital Design Studio keeps the 20 newest runs. If a source, an included file or a Verilog setting changes during a run, the run is marked as failed; run it again.

Fix common errors

Symptom	What to do
The example did not open by itself	The automatic start is for new users only. Choose Open example on Projects on this PC (Local).
"The example project could not be opened. To try again, choose Open example in Local."	Choose Open example in Local. While the example does not exist, later starts of the app also try again, up to three attempts in total.
There is no Testbench button	In the Windows app, open a project on this PC and use the Testbench view to run its testbench.
"No testbench found. …"	A testbench is a module without ports that no other module instantiates, such as `module counter_tb;`. Save the file and choose Rescan.
The download fails or stalls	Check the connection, proxy or firewall for github.com, release-assets.githubusercontent.com and objects.githubusercontent.com, then press Run again. The download resumes where it stopped.
Antivirus software blocked a file, or Icarus Verilog does not start	Keep the exact security-software message and verify the official download and expected hash. Do not disable protection or add a broad exclusion just to force the run. Ask support or your administrator to review the specific detection before retrying.
Not enough free disk space	Free the amount shown in the message and try again.
Verilator cannot be selected	Verilator needs a C++ compiler and make on this PC, for example MSYS2 UCRT64 with `pacman -S mingw-w64-ucrt-x86_64-gcc mingw-w64-ucrt-x86_64-make`. Icarus Verilog works without them.
"This run wrote no waveform. …"	Add `$dumpfile("name.vcd")` and `$dumpvars` to the testbench. Give a file name without a folder: only a waveform written in the run's own folder is opened.
The waveform is larger than 32 MiB	Narrow `$dumpvars` or shorten the run.

Include files and macros

Keep included .svh and .vh headers inside the project. RTL compilation, Icarus Verilog and Verilator search the project root first, then Include directories in the saved order, then discovered source folders in name order. If another header next to the including file differs, Problems and Simulator log identify both paths and the header used.
If Simulator log shows that an included file was not found, add its folder, relative to the project root, to Include directories under Project (Flow Navigator → Project Manager → Settings → Project → Include directories), then press Run again. Enter macros in Project → Defines, one NAME or NAME=VALUE per line.
Including a file from outside the project fails the run before the simulation starts. Simulator log then says "… is outside the project: copy it into the project and include it from there".
An Include directories entry that points outside the project or contains .., or an invalid macro name in Defines, stops the run with a message that names the entry. Correct or remove it. A listed folder that does not exist is skipped with a warning in Simulator log.
Changed settings apply from the next run. Editor diagnostics use them after you reopen the project.

Next steps

Change the testbench, for example the number of enabled clock cycles and the expected count, then press Run again. Run saves your edits first.
Install a C++ compiler and make, choose Verilator in Simulator and compare the result with Icarus Verilog.
Run your own design: on Projects on this PC, choose Open project folder or New project. Add your .v and .sv sources and a testbench that writes a waveform with $dumpfile and $dumpvars. Then open the RTL simulation tab from Flow Navigator → Simulation → Run Simulation → Open Simulation setup. If you have not signed in, Run Simulation opens the tab directly.
For editing and saving projects, see Workspace; for Verilog files, see Verilog.

For platform differences and the company AI, storage and account conditions that apply separately from this local simulation, see the support guide.

Environment support