First RTL simulation in Digital Design Studio#

Prepare a two-bit counter, check its synchronous reset, and compare every clock edge with a verified native CLI result.

Overview#

Use this exercise after the first saved-file check. It shows a two-bit counter starting at 3, resetting to 0 at the first rising clock edge, and wrapping from 3 back to 0. Inputs come from JSON, not a testbench.

The complete counter request below passed Preflight and Run using the Linux x86_64 alti-rtl executable from engine bundle 0.1.10. Every rising and falling output and the VCD values were checked. Windows 1.0.37 was separately checked with a one-DFF GUI example: four cycles, eight transitions, final q=1. This counter has not been separately qualified through the Windows or Cloud GUI.

Choose the execution path#

Path

Requirement

Boundary

Windows Desktop

Verified 1.0.37 package, local project, normal execution entitlement

The native panel reads saved project files; save edits before Preflight and Run

Linux CLI

Already verified alti-rtl from the 0.1.10 engine bundle, x86_64 Linux

Separate executable; do not assume the older alti CLI Preview archive contains this version

Cloud browser

An accessible Cloud project for reading or editing

The Desktop native RTL panel and executable are not a browser execution path

Check Downloads for public package availability. This guide does not provide a trust bypass or announce a Microsoft Store release. Editor access does not grant native execution entitlement. No Cloud Compute, Evolve, or paid job is required for the local exercise.

Prepare one saved source file#

Create a new exercise directory and save the following as rtl/top.sv. Open that directory from Local projects → Open existing project… on Desktop. Keep only this exercise’s top in the project; do not mix in other examples, generated testbenches, or files containing initial and delay controls.

SystemVerilog
module top (
    input logic clk,
    input logic rst,
    output logic [1:0] count
);
    always_ff @(posedge clk)
        if (rst) count <= 2'b00;
        else count <= count + 2'b01;
endmodule

The initial register values are [true,true], or binary 11. Although rst is already high at time 0, count stays at 3 until the first rising edge: this is a synchronous reset. The two-bit result then increments modulo 4.

Enter the Desktop inputs#

Open New analysis and choose Two-state single-clock v1 under RTL simulation contract, even if the initial choice is the four-state v2 contract. Use these values in RTL Simulation.

Field

Value

Clock port

clk

Clock period (ps)

1000

Reset port (optional)

rst

Reset behavior

Active high

Reset assertion cycles

1

Maximum cycles

5

Maximum time (ps)

5000

Initial register values JSON (engine register order, lsb0)

[true,true]

Paste this array into Cycle input stimulus JSON (complete non-control inputs, lsb0). The engine supplies clk and the configured rst; the five input maps are deliberately empty. Do not paste the full CLI request into this field.

JSON
[
  {"inputs": {}},
  {"inputs": {}},
  {"inputs": {}},
  {"inputs": {}},
  {"inputs": {}}
]

  1. Save rtl/top.sv, then select Preflight. Expect top top, two scalar inputs, one two-bit output, two registers, five cycles, and ten transitions.

  2. Review Elaborated interface, Trace bounds, and Semantic boundary. Preflight checks admission; it does not execute the requested simulation.

  3. Select Run RTL simulation. Compare Final trace summary with the expected result below.

  4. Inspect Trace artifact, VCD waveform metadata, and Execution provenance. This panel displays waveform metadata; it does not automatically open an interactive waveform viewer.

  5. If Persisted full receipt is present, use Recent RTL simulation receipts → Refresh → Read followed by the receipt ID to inspect the saved result. Read is not a new Run, and an identical input may reuse an existing receipt identity and creation time.

Run the verified CLI request#

For the Linux path, save the following complete request as counter-request.json in a new directory. It includes the same source text; changing rtl/top.sv alone does not update this embedded source. Keep both copies in agreement when making a new exercise.

JSON
{
  "schema": "altifigence.rtl.operation-request.v1",
  "version": 1,
  "operationId": "altifigence.rtl.simulate.v1",
  "request": {
    "top": "top",
    "sources": [
      {
        "path": "rtl/top.sv",
        "source": "module top (\n    input logic clk,\n    input logic rst,\n    output logic [1:0] count\n);\n    always_ff @(posedge clk)\n        if (rst) count <= 2'b00;\n        else count <= count + 2'b01;\nendmodule\n"
      }
    ],
    "clock": {"port": "clk", "periodPs": 1000},
    "initialRegisterValues": [true, true],
    "cycles": [
      {"inputs": {}},
      {"inputs": {}},
      {"inputs": {}},
      {"inputs": {}},
      {"inputs": {}}
    ],
    "limits": {"maxCycles": 5, "maxTimePs": 5000},
    "reset": {"port": "rst", "activeLevel": "active_high", "assertCycles": 1}
  }
}

Here ./alti-rtl means the matching, already verified executable. Adjust that path to its actual location. Use new output filenames so a previous result is not overwritten; continue to Run only after Preflight exits successfully.

Bash
./alti-rtl simulate preflight counter-request.json > counter-preflight.json
./alti-rtl simulate run counter-request.json > counter-result.json

Both commands exited 0 for this request. Preflight reports admitted: true. Run returns an altifigence.rtl.operation-result.v1 envelope with the simulation artifact and provenance. Preserve the full result, including its recorded waveform and hashes, rather than treating a successful process exit alone as proof that every intermediate value was correct.

Compare reset and every edge#

In JSON, true is 1 and false is 0. Port vectors are least-significant-bit first: binary 10 is [false,true]. Initial values follow the register order reported by Preflight, not an arbitrary port order. Recheck that order and count after changing the circuit.

Time (ps)

Event

rst

count, most-significant bit first

0

Initial state, clock low

1

11

500

Rising edge applies synchronous reset

1

00

1000

Falling edge releases reset

0

00

1500 / 2000

Rising / falling

0

01 / 01

2500 / 3000

Rising / falling

0

10 / 10

3500 / 4000

Rising / falling

0

11 / 11

4500 / 5000

Rising edge wraps / falling

0

00 / 00

Expected summary: 5 cycles, 10 transitions, 5000 ps, final count=[false,false]. At falling edges, the next cycle’s inputs are applied; the last falling edge retains the last input. A combinational output can change there even when register outputs wait for the next rising edge.

Current semantic limits and recovery#

The selected v1 contract uses two-state 0/1 values, a single scalar clock, positive-edge storage, and a bounded synthesizable subset. Clock period labels VCD time; it is not propagation delay, setup/hold analysis, maximum frequency, or physical timing signoff. Do not put X/Z, multiple clocks, negative-edge storage, initial, #delay, classes, DPI, UVM, or assertion testbenches in this v1 request. Other contracts have their own admission rules.

Symptom

Next step

Native adapter unavailable or the panel is absent

Confirm that this is a supported Desktop project window; do not substitute a Cloud or unavailable action

Entitlement denied

Use normal sign-in and product entitlement support; editor access is not execution authorization

Exactly one inferred top required

Use a separate directory containing only this example; preserve other work elsewhere

Initial register value count or vector width rejected

Run Preflight again and match the reported registers, port names, and least-significant-bit order

logic-netlist-0 rejected

The current event simulator rejects the pure combinational netlist schema; use the documented sequential example rather than changing a schema label

logic-netlist-1 rejected by an older binary

Check the actual executable and product version; use the supported update path

JSON, cycle, or time bound error

Restore the complete five-cycle array and the matching 5 / 5000 limits

Result differs after editing

Save the right project file; for CLI also update the embedded source, then Preflight and Run again

This exercise establishes a small native RTL result, not full SystemVerilog conformance, synthesis equivalence, FPGA implementation, ASIC signoff, or all GUI feature parity. Continue to Analysis Views to understand which saved artifacts a viewer actually reads.