ASIC process
Follow the stages from reviewed RTL through implementation and signoff.
Overview
The ASIC flow starts with reviewed RTL, then moves through synthesis, physical implementation, analysis, and signoff. Each stage should leave inputs, reports, and tool versions that can be reviewed later.
Stages
Stage | Required context | Observable evidence |
|---|---|---|
RTL readiness | Source, constraints, clocks, resets, and verification status | Diagnostics and an accepted baseline |
Synthesis | Target libraries, constraints, and supported toolchain | Netlist, reports, warnings, and tool versions |
Physical implementation | Floorplan, placement, clock, routing, and process inputs | Stage reports, artifacts, and constraint results |
Analysis | Timing, power, area, congestion, integrity, and reliability inputs | Reviewable metrics, violations, and methodology |
Signoff | Foundry rules, corners, tools, and acceptance criteria | Reproducible signoff reports |
How it works
Altifigence products organize project inputs, run tools available on the selected machine or runner, and keep reports and artifacts together for review.
Collect the technology inputs
Identify the authorized PDK/library release and the target process, voltage and temperature corners. Record the Liberty timing/power libraries, LEF/technology data, extraction models, constraints and rule decks required by your chosen tools. Preserve their versions and usage terms with the project; a generic target name does not provide those files.
Review each handoff
Handoff | Check before continuing |
|---|---|
RTL to synthesis | Top module, clocks/resets, elaboration, test coverage and constraints. |
Synthesis to physical implementation | Mapped netlist, library/corner identity, timing constraints, area and unresolved warnings. |
Placement/routing to extracted analysis | Connectivity, routing completion, parasitics and selected extraction corner. |
Analysis to signoff | Complete required corners, timing/power/integrity checks and approved waivers. |
Signoff to delivery | Final layout/netlist/checksum set, required reports and foundry/customer acceptance. |
DDS GDS viewing, generic RTL metrics, bounded PX calculations and ALcad process models answer specific inspection or modeling questions. Use the qualified tools and required reports for DRC, LVS, timing, reliability and foundry acceptance. Keep uncomputed or unsupported values visibly unavailable.
Archive a reproducible result
Keep a manifest linking the exact source, constraints, technology inputs, tool versions/options, execution environment and resulting artifact hashes. Save failing reports and waivers as well as passing reports. Re-run the affected stages when any relevant input changes; opening an old report does not recompute it for a new revision.