ASIC process

Follow the stages from reviewed RTL through implementation and signoff.

Overview

The ASIC flow starts with reviewed RTL, then moves through synthesis, physical implementation, analysis, and signoff. Each stage should leave inputs, reports, and tool versions that can be reviewed later.

Stages

Stage	Required context	Observable evidence
RTL readiness	Source, constraints, clocks, resets, and verification status	Diagnostics and an accepted baseline
Synthesis	Target libraries, constraints, and supported toolchain	Netlist, reports, warnings, and tool versions
Physical implementation	Floorplan, placement, clock, routing, and process inputs	Stage reports, artifacts, and constraint results
Analysis	Timing, power, area, congestion, integrity, and reliability inputs	Reviewable metrics, violations, and methodology
Signoff	Foundry rules, corners, tools, and acceptance criteria	Reproducible signoff reports or an explicit incomplete state

How it works

Altifigence products organize project inputs, run tools available on the selected machine or runner, and keep reports and artifacts together for review.

Incomplete Stages

If a tool, licence, process input, or signoff check is missing, the stage remains incomplete. Do not replace a missing report with an estimated pass.