Verilog in Digital Design Studio

Digital Design Studio 2.0.2: Verilog in Digital Design Studio. Check the selected host, account permissions and current support before use.

Overview

Digital Design Studio recognizes .v and .vh files so you can open, edit, and save Verilog source alongside .sv and .svh files. A .v file can also be an explicit RTL project input used by project discovery and the Outline.

Start with a Verilog file

  1. Open an existing project directory that contains a .v source file.

  2. Select the file from Explorer or Go to File.

  3. Edit and save it with Save File or Ctrl+S.

  4. Reopen the file and confirm that the saved change is present.

Header files using .vh are recognized and editable. The native project source-root path is explicitly defined for .sv and .v; a header is normally reached through the project file tree or an include relationship rather than treated as a standalone top.

Language Coverage

The editor recognizes Verilog files, but parser, elaboration, simulation, synthesis, timing-model, PLI/VPI, and protected-source support vary by construct and release. Check diagnostics from the action you run; editor support for a file does not mean every downstream tool accepts every construct.

IEEE lists IEEE 1364-2005 as a superseded standard that was folded into the unified SystemVerilog standard line. Verilog source remains a supported project format here, so we call this Verilog support, not a separate “legacy mode.” See the official IEEE 1364-2005 status page for the standard’s publication status.

Related pages

Prepare a source set

  1. Save the top module and all required .v/.sv sources.

  2. Set the top module when needed. Save the project’s include directories and defines for supported v2.0.2 native compilation, saved-source capture and OSS simulation. Keep headers inside the project and check the operation’s diagnostics. These settings do not enable an unavailable Cloud operation.

  3. Check case-sensitive module and signal names, duplicate definitions and unresolved includes.

  4. Run the operation and use its diagnostics to locate unsupported constructs. Editor highlighting alone does not establish simulation coverage.

For the supported Windows OSS simulator flow, see First RTL simulation. The 1.0.89.4 Windows and Cloud limitations described by that older release are separate from the v2.0.2 Windows flow. The alti sv frontend and alti sv review engine commands still need the separately installed Linux CLI; their existence does not enable a Windows command.

Save preprocessing settings

In Digital Design Studio 2.0.2, native RTL compilation, source capture and the OSS Icarus Verilog and Verilator runs use saved include directories and defines. In Flow Navigator → Project Manager → Settings, find Project compile inputs. Enter one item per line in Include directories and Defines, save, then run the supported operation again. A project value takes precedence over the IDE default; an explicitly empty project list clears inherited values.

  • Include directories must stay inside the project, such as rtl/include or .. Missing folders produce a warning and are skipped. Parent traversal, paths outside the project, symbolic links and junctions are rejected.

  • Defines use NAME or NAME=VALUE, such as SIMULATION or WIDTH=8, without a command-line -D prefix. A name starts with a letter or underscore and continues with letters, digits, underscores or $. Conflicting values for one name are rejected; identical entries are deduplicated.

  • Each field accepts up to 1,024 entries, each 1–256 UTF-8 bytes without control characters.

Header search order

RTL compilation, Icarus Verilog and Verilator search in the same order: the project root, your saved include directories in their listed order, then discovered source folders in name order. If a different header next to the including file would otherwise be chosen, Problems and the run log warn about the two paths and identify the file used. Remove ambiguous duplicates when possible.

Save sources and headers before execution. The Testbench Run action saves edited Verilog sources first; other operations use their documented saved-input behavior. A settings or source change can invalidate an earlier capture, estimate or running result. Run again with the saved inputs. Project settings do not enable an unavailable Cloud operation. For a missing header, check the selected project, path, case, saved settings and simulator installation.

2.0.2 environment support