Elaborate CX and export a decoder

Altifigence CLI 0.1.9 on Linux reads native CX source from standard input for ISA operations. Start with a single ADD instruction so you can inspect the instruction format, register operands, encoding, and execution expression together. Save the following source as add.cx in your working directory. The register file contains 32 registers, each 32 bits wide, and x0 reads as zero.

Require exit status 0 before reading a saved result. Keep standard error separately and inspect the result fields described below.

Save a CX instruction

arch CX-Core {
    word = 32 bits
    address = 32 bits
    endian = little
}
regfile gpr {
    count = 32
    width = 32 bits
    x0 = hardwired 0
}
format R = 32 bits {
    funct7 @ 31..25
    rs2 @ 24..20
    rs1 @ 19..15
    funct3 @ 14..12
    rd @ 11..7
    opcode @ 6..0
}
operand gpr (5 bits) {
    reads gpr[@]
    writes gpr[@]
    asm "x{@}"
}
instruction ADD uses R {
    reads rs1, rs2 : gpr
    writes rd : gpr
    encode opcode=0b0110011, funct3=0b000, funct7=0b0000000
    asm "add {rd}, {rs1}, {rs2}"
    exec rd <- rs1 +wrap rs2
}

The R format assigns every encoding field an explicit bit range. ADD fixes the opcode, funct3, and funct7 values while the source and destination registers occupy their named fields. Its assembly spelling uses the operand format x followed by the register index. Keep this source file as the shared input for elaboration and both exports.

Elaborate and export

alti isa elaborate < add.cx
alti isa export-decoder --language sv < add.cx > decoder-result.txt
alti isa export-reference --format md --title "ADD reference" < add.cx > reference-result.txt

Run elaboration first and check that its JSON result has ok: true before exporting. Source errors appear in diagnostics with ok: false. The decoder export selects SystemVerilog; the reference export selects Markdown. The saved command output contains the generated result for inspection. Keep add.cx beside these results so later changes can be traced back to their source. If elaboration reports ok: false, use its diagnostic to correct that file, repeat elaboration, and regenerate both outputs from the corrected version.

Inspect the export result

The decoder output is a JSON export result. These selected fields identify the generated file; content contains its SystemVerilog text. The reference result uses filename cx_reference.md and contains the Markdown text in content.

{"schema":"cx-export/1","ok":true,"kind":"decoder","format":"sv","filename":"cx_decoder.sv","mime_type":"text/x-systemverilog","word_bits":32,"instruction_count":1}

If adding --disassembler to the SystemVerilog export produces the error disassembler export supports C and Rust, remove --disassembler and repeat the shown SystemVerilog command.