Use vFactory: explore a fab and follow a design to wafer

Open vFactory in Digital Design Studio, walk through the reference fab, replay a simulation, inspect EUV models and follow a Cloud GDS layout to a virtual wafer.

Open vFactory

  1. vFactory is the wafer-process and fab area inside Digital Design Studio, alongside DDS and ALcad.

  2. In the product menu, choose vFactory → Wafer Process & Fab; the fab scene is enabled by default.

  3. The interface is available in Cloud and the Windows and Linux apps; project-file actions depend on the selected host.

  4. Start in Reference fab, or select Process models, Design to wafer, EUV calculation or EUV clip for the task.

  5. The original reference example contains 300 tools on four levels, with an adjustable 200–400-tool layout and explicit assumptions for its numerical values.

Open vFactory from the product menu.

Open vFactory from the product menu.

Walk and choose a view

  1. Use 2D map, 3D map, Top view, Walk or Dollhouse to inspect the fab.

  2. In Walk, focus the viewport and use W/S to move forward/back, A/D to sidestep and Shift to run.

  3. Drag in the 3D view to look around.

  4. Approach a door and press E; closed doors, walls and equipment block the walking route.

  5. Under Stairs / elevator, choose Destination level and Connection, use Walk to connection and then Change level when you arrive.

  6. Walk to the EUV area and approach a scanner until Look inside · EUV scanner {number} appears.

Walk through the reference fab and approach the EUV lab.

Walk through the reference fab and approach the EUV lab.

Run a simulation and replay lots

  1. In Process models, choose Seeded fab simulation (v2), review the model inputs and use Run simulation when it is available.

  2. The same model and seed reproduce the same run; timings, failures, maintenance and batching come from the supplied model.

  3. For a completed run with recorded events, use Play simulation, Pause simulation, Restart playback and Playback speed, from 1× to 100,000×.

  4. Select a lot or search its exact ID to inspect its recorded state at the selected simulation time; select a tool separately to inspect its state.

  5. The released default simulation path replays recorded lots and tool states; it does not generate AMHS vehicle events or replay OHT vehicles. A rail layout alone does not create vehicle simulation.

Inspect a selected lot during recorded fab playback.

Inspect a selected lot during recorded fab playback.

Inspect the EUV scanner and calculation

  1. Choose Look inside · EUV scanner {number} in Walk to open the structure lab, and use Close inside view or Escape to return.

  2. Keep Reconstruction · assumptions in mind: the structure uses public information and assumed dimensions, rather than manufacturing CAD.

  3. In EUV calculation, review an editable preset and choose Calculate EUV to inspect the source-to-wafer power and photon budget.

  4. Treat scan speed, wafers per hour and the optical results as uncalibrated calculations with labelled assumptions, rather than measured equipment throughput.

  5. The 12.5–14.5 nm sweep holds the 13.5 nm optical indices fixed; it is not a measured spectrum or dispersion model.

Inspect the reconstructed EUV scanner with its assumption label.

Inspect the reconstructed EUV scanner with its assumption label.

Read an assumption-based EUV light budget.

Read an assumption-based EUV light budget.

Send a design and read the virtual wafer

  1. In a capable Cloud project's DDS GDS viewer, choose Send to vFactory for the projected structure to open Design to wafer with that design; nothing runs until you choose Run design to wafer.

  2. The handoff begins with one 25-wafer lot; choose the Reference fab route, review the lot count, wafer count and release interval as editable assumptions, and use Calculate preview to check the wafer map and yield estimates before you run.

  3. The 300 mm wafer map uses the GDS bounds for die size and includes scribe spacing and edge exclusion.

  4. Compare Poisson, Murphy and negative-binomial yield estimates using the displayed defect-density assumption; these are estimates, not measured good-die counts.

  5. Read Lot completion and delivery as seconds from simulation start; unfinished lots have no completion or delivery estimate, and overall delivery requires all requested lots to finish.

The Design to wafer tab without a design source. A message says there is no design source and asks you to send an existing DDS design or import a tapeout source package. The screen also shows the Import DDS / tapeout source button, the inputs for geometry, yield and lot release, the Cleanroom environment · Assumptions sliders for ISO class and downflow, and the unavailable Calculate preview and Run design to wafer buttons.

Until a design arrives, Design to wafer shows that there is no design source, together with its editable assumptions. Calculate preview and Run design to wafer stay unavailable.

Read the wafer map, yield assumptions and simulated lot delivery.

Read the wafer map, yield assumptions and simulated lot delivery.

  1. Use Follow lot in 3D for a newly simulated lot; completion or selection of another lot stops following, and reopened summary files do not contain replay events.

  2. A new DDS handoff links ISO class and downflow to the fab environment sliders; imported or reopened inputs keep their own assumptions until explicitly linked.

Check the Design to wafer inputs and keep ISO class and downflow linked to the fab environment sliders.

Check the Design to wafer inputs and keep ISO class and downflow linked to the fab environment sliders.

  1. Changing those linked sliders recalculates concentration, environment D0, yield and expected good dies without rerunning the fab; save the revised result explicitly when project saving is supported.

  2. ISO class is a particle-concentration proxy, not a measured distribution or certification; downflow is part of an uncalibrated deposition assumption.

  3. Temperature, humidity, pressure and vibration have no modeled particle, defect, yield or thermal effect.

Import your own files

  1. For a layout preview, use Fab setup → Import fab layout with a complete fab-model/v1 or fab-model/v2 JSON file.

  2. For source-data conversion, choose Import fab data in the seeded v2 model and review Import diagnostics before running; incomplete or unsupported source semantics must be resolved first.

  3. The source-file importer accepts supported .asd, .xlsx, .cf, .os, .pr, .rw, .ts, .vr, .rte, .txt and .csv files, plus options.def, with up to 64 files, 32 MiB per file and 64 MiB total.

  4. Design to wafer separately accepts a DDS/tapeout source JSON package and optional assembly/test duration inputs; its JSON imports are limited to 1 MiB.

  5. Obtain import-only external datasets yourself; the product does not bundle those datasets, and its supplied fab example is synthetic.

  6. External tours, recordings and vendor pages are viewing references only; their screenshots, video, CAD and logos are not bundled fab assets.

Limits to keep in view

  1. On Linux desktop, the WebGL2 fallback uses the Low tier; where neither WebGPU nor WebGL2 is usable, the fab shows the true-scale 2D plan.

  2. EUV clip computes a local thin-mask aerial image; Cloud imaging is not available in the published release, so use local tiling within device limits.

  3. The EUV structure viewer explains reconstructed optical structure, and its illustrative rays are not an electromagnetic, imaging, thermal or vibration simulation.

  4. Fab cycle and delivery times, yield estimates and the EUV budget are model results with assumptions, not manufacturing signoff or real delivery promises.

  5. The release notes record shared GPU memory growth on Intel Iris Xe after repeated EUV inside-view opens or Medium/Low quality switches.