Design to wafer inputs

Look up source-package fields, numeric input ranges and backend JSON values.

This reference applies to vFactory in Cloud 2.1.2.10 and Windows 2.1.2.3.

Use these values in Design to wafer. Numeric inputs use finite numbers; lot and wafer counts use whole numbers.

Source package

Import DDS / tapeout source accepts a JSON file up to 1 MiB (1048576 bytes): a serialized DesignToWaferInput or {source: DesignSource}. A source-only package uses the default assumptions. The validated input fits within 32768 bytes of canonical JSON.

DesignSource contains projectId, gdsPath, inputSha256, structure and boundsM. Use a .gds or .gdsii host path, a 64-character lowercase hexadecimal SHA-256 and bounds [minX, minY, maxX, maxY] in metres with positive width and height. Geometry uses an integer nanometre grid.

In Cloud, each die side is accepted from 1.5 to 20 mm, and Reference fab route offers logic-a and logic-b, with logic-a selected by default. Windows uses logic-a.

Numeric values

The final lot release time, (lot count − 1) × release interval, is accepted up to 31536000 seconds. Geometry and derived values are validated during preview calculation and execution.

Input

Accepted values

Scribe (µm)

0–10000

Edge exclusion (mm)

0 ≤ value < 150

User D0 (defects/cm²) · Assumption

0–1000000

Clustering α

0 < value ≤ 1000000

Lot count

1–50

Wafers per lot

1–1000

Release interval (s)

0–31536000

ISO class · Assumption

1–9, including fractional values

Threshold D (µm)

0.1–5

Downflow (m/s), Settling speed (m/s), Exposure (s)

0–9007199254740991

Deposition fraction (0–1), Killer fraction (0–1)

0–1

Backend JSON

Import backend JSON accepts schema altifigence.vfactory-backend/v1, a name and steps. Supply 1–32 uniquely named steps, each with name and durationS. Each duration and their sum are accepted from 0 to 31536000 seconds. Model and step names use 1–256 characters, with trimmed ends and ASCII control characters excluded.

Related guides

Use vFactory: explore a fab and follow a design to wafer

Reference-fab layouts, process data and results use example assumptions.