Navigate the RTL outline on Windows

Find a signal or instance in the current file and open its source line on Windows.

Use Digital Design Studio 2.1.2.3 for Windows. Open and select a Verilog or SystemVerilog source file in a local project.

Open the outline

  1. Press Ctrl+Shift+P to open the command palette, then run Show Outline.

  2. In the right panel, expand a module to inspect its inputs, outputs, internal signals and instances.

  3. Select a signal or instance row to move the editor to its declaration line.

Search the current file's outline

  1. Enter part of a name in the outline panel's search field.

  2. Select a matching signal or instance row to open its source line. Clear the search to show the full outline again.